Matching Data Type

SystemVerilog
1

Hi,

In the following example, Is reference formal argument ref_ip have equivalent type to the actual argument ip.


typedef bit signed tp1;
task automatic print(ref tp1 [7:0] ref_ip);
    #1 ip = '1;
    #1 $display(ip);
endtask

module test();
  bit  signed [7:0] ip ;
initial begin
   print(ip);
   #3   $display ("From TB : ", $typename(ip));
end
2

In reply to SumitGoel:

These types are not equivalent according to section 6.22.2.c of the 1800-2012 LRM. Both actual and formal arguments must be either both signed or both unsigned. And according to section 7.4.1, a packed array has to be declared as signed for the array as an integral type to be viewed as signed. In your formal argument declaration, the individual elements of the packed array are signed, but not the array as a whole.

3

In reply to dave_59:

Thanks Dave!!