Loops on conditions in Assertions

Hi all,

I need a small help for assertion for the below requirement

"a" and "b" are two signals which are of one bit and they are of logic type with "x" as initial value. 
At time t1, a becomes 1,
At time t2, b becomes 0,
At time t3, b becomes 1,
At time t4, b becomes 0,
At time t5, b becomes 1,
At time t6, b becomes 0,
At time t7, b becomes x.

I want to check high and Low pulsewidth of b is same and also all the High pulse widths should be equal and all the low pulse widths should be equal till this scenario ends.
Can someone tell me how this assertion looks like. How we can loop through for all high/low pulse widths? Or else Do I need to have a seperate assertion for each high/low pulsewidth?