For loop in sv

SystemVerilog
1

Hi can anyone explain how this circuit will work. Suppose that b[5] is high and any other element in b is low, what is the value of ptr. What will happy if in the next clk cycle b[6] become high and b[5] become low.

always_comb begin
   ptk = '0;
   for (int i = 0; i < 8; i++)begin
         if(~key)begin
              ptr = 3'(i);
              key = b[i]; 
         end
   end
end
2

In reply to nomiisalao:

There are a couple of problems with this code.

Is ptk/ptr a typo?
What is the initial value of key? It needs a value otherwise this is not combinational logic.