For loop execution

SystemVerilog
,
1

I wrote a program for creation of a linked list and displaying it. I have used a for loop for creating multiple nodes. Since SystemVerilog for loop doesn’t operate like c, I am able to add only one node using the for loop.

// Code your testbench here
// or browse Examples
class Node;
  int data;
  Node next;
endclass: Node

module krishna;
  
  int a[5] = '{3,4,2,4,5};
  
  function Node create (int a[], int n);
    Node current = new();
    Node prev;
    Node head;
    head = current;
    
    current.data = a[0];
    current.next = null;
    
    prev = current;
    
    for(int i=1; i<n; i++) begin
        Node current = new();
        prev.next = current;
      	current.data = a[i];
        current.next = null;
        prev = current;
    end
    return head;
  endfunction
  
  function void display(Node n);
    while(n!=null) begin
      $display("%d",n.data);
      n = n.next;
    end
  endfunction
  
  initial begin
    Node head = create(a, 5);
    display(head);
  end
  
endmodule : krishna

Output is 3 and 5 instead of 3 4 2 4 5

2

In reply to Krishna9:


class Node;
  int data;
  Node next;
endclass: Node
 
module krishna;
 
  int a[5] = '{3,4,2,4,5};
 
  function Node create (int a[], int n);
    Node current;
    Node prev;
    Node head;
 
    current = new();
    current.data = a[0];
    current.next = null;
 
    head = current;
    prev = current;
 
    for(int i=1; i<n; i++) begin
      current = new();
      current.data = a[i];
      current.next = null;

      prev.next = current;
      prev = current;
      $display("Added %0d\n", current.data); 
    end
    return head;
  endfunction
 
  function void display(Node n);
    while(n!=null) begin
      $display("%d",n.data);
      n = n.next;
    end
  endfunction
 
  initial begin
    Node head = create(a, 5);
    display(head);
  end
 
endmodule : krishna