I would like to know how loop exit conditions in Systemverilog are evaluated.
For example, if I have a for loop
for (idx = 0; idx < queue.size();idx++)
Now within this loop, if I delete entries in the queue, would the compiler check size for every iteration or just once.
My initial hunch was that this is a static evaluation by the compiler and it would loop queue.size() times, as evaluated initially.
But I wrote a small piece of code and looks like compiler evaluates queue.size() for every iteration.
Below is the code:
module x;
integer Q[$] = { 1,2, 3, 5, 6, 7, 8, 9, 10};
initial begin
for (int idx = 0; idx <= Q.size(); idx++) begin
$display("idx %d val %d size %d", idx, Q[idx], Q.size());
Q.delete(idx);
end
end
endmoduleBelow is the output:
Quote:
idx 0 val 1 size 9
idx 1 val 3 size 8
idx 2 val 6 size 7
idx 3 val 8 size 6
idx 4 val 10 size 5
Can anyone provide more insight including any LRM section reference?