For loop to assign multiple variables

SystemVerilog
,
1

Hi,
I am coding some coverpoints and I have variables like

bit [31:0] var_inst0;
bit [31:0] var_inst1;
bit [31:0] var_inst2;
.
.
bit [31:0] var_inst99;

I have to assign these variables to RTL signals in my TB.
Ex:

assign var_inst0 = dut.module1.module2.reg_cfg[0].var;
assign var_inst1 = dut.module1.module2.reg_cfg[1].var;

and so on. Is there a way to write a for loop to assign all these variables at once instead of writing 100 assign statements.

Thanks.

2

In reply to sj1992:

That nagging suspicion that must be gnawing within your inner voice “Stop using cut/paste and properly use multi-dimensional arrays”:

bit [ 31 : 0 ] var_inst [ 0 : 99 ]

That solves your problem, among other things - like a 100/1 code reduction.

Edit to add: Then use a generate loop:

for( genvar i = 0; i < 100; i++ )
begin : iter_i
  assign var_inst[ i ] = dut.module1.module2.reg_cfg[ i ].var;
end

Regards,
Mark

3

In reply to Mark Curry:

Hi Mark ,

Those variables(var_inst0,var_inst1…) and their corresponding coverpoints are generated automatically from an excel sheet using a perl script. So I would have to manually change wherever these variables are being used. So is there any way to implement the assignment using for loop?

Thanks.

4

In reply to sj1992:

In reply to Mark Curry: So is there any way to implement the assignment using for loop?
Thanks.

Yes, Fix your PERL script. Either have it create an array as Mark suggested above, or have it generate the assignments for you.
SystemVerilog is a compiled language and you cannot create identifier names during runtime. (Same as C/C++/Basic)

5

In reply to dave_59:

Hi Dave,

I will try that but can we write the assign statements using defines?
Ex:

`define M_SUB(i) ``i
for( genvar i = 0; i < 100; i++ )
begin : iter_i
  assign var_inst`M_SUB(i)	=   dut.module1.module2.reg_cfg[i].var;
end

Thanks.

6

In reply to sj1992:

No. Macros get expanded before processing any SystemVerilog code.