Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Functional Safety
      • Portable Test and Stimulus
      • Design & Verification Languages

    • Methodologies

      • Coverage
      • UVM - Universal Verification Methodology
      • FPGA Verification

    • Techniques & Tools

      • Acceleration
      • Formal-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Verification IP
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Introduction to DO-254
      • Portable Stimulus Basics
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • AMS Forum
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizon - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Optimizing Questa Performance - Oct. 25th
      • Practical "must have" Applications for SLEC - Fremont, Oct. 25th
      • Events Calendar

    • On Demand Seminars

      • Portable Simulus
      • Debug
      • Coverage
      • FPGA Verification
      • Stimulus Generation
      • UVM Forum
      • All On-Demand Seminars

    • Recording Archive

      • Portable Stimulus from IP to SoC
      • UVM 1800.2 & Updated UVM Cookbook
      • Wilson Research Group - 2018 Results
      • What Is Formal, And How It Works Under-the-Hood
      • DAC & DVCon
      • Silicon Valley Design & Verification IP Forum
      • All Recordings

    • Mentor Training Center

      • SystemVerilog Assertions
      • SystemVerilog for Verification
      • SystemVerilog UVM
      • SystemVerilog UVM Advanced
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Vectors and Arrays
      • SystemVerilog Advanced OOP
      • SystemVerilog Functional Coverage
      • UVM Transactions and Sequences
      • UVM Monitors and Agents
      • UVM Tests and Complex Sequences
      • Basic CDC Verification
      • Finite State Machine Viewer
      • Functional Verification Library
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - June 2018
      • Verification Horizons - March 2018
      • Verification Horizons - December 2017
      • Verification Horizons - June 2017
      • Verification Horizons - March 2017
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • SystemVerilog
      • Functional Verification Library
Ask a Question
SystemVerilog
  • Home /
  • Forums /
  • SystemVerilog /
  • For loop and a random variable

For loop and a random variable

SystemVerilog 3180
constraint for loop 3
syed taahir ahmed
syed taahir ahmed
Full Access
68 posts
May 22, 2018 at 7:38 am

HI ,

I have a scenario where i have to randomize the loop count and randomize the variable such the loop count should not be wasted due to duplication of randomization of variable.

for Eg:: 

sa_entry_row        = $urandom_range(1,5);//Randomizing  The number of times add entries
                      for(int j=0; j<sa_entry_row; j++) begin
                      entry_add_index = $urandom_range(0,($size(test_entries_add)-1));//Randomizing the SA_entry index
                      //this condition will check existing added list in queue and avoid duplication
                      if (!(entry_add_index inside test_entries_added)) begin

if we see the code, sa_entry_row count gets unused if the entry_add_index is already existing, how should i make sure that entry_add_index is unique for each sa_entry_row?

Thanks

Replies

Log In to Reply
dave_59
dave_59
Forum Moderator
5853 posts
May 22, 2018 at 10:32 am

In reply to syed taahir ahmed:

It would really help to show the declarations of all variables involved and what they represent.

From what I can figure out, you should be using constraints. 

randomize (entry_add_index) with {
    entry_add_index <$size(test_entries_add);
    unique {entry_add_index,test_entries_added};
}
syed taahir ahmed
syed taahir ahmed
Full Access
68 posts
May 22, 2018 at 10:42 am

In reply to dave_59:

This is my full code. The issue is for eg:: when i randomize sa_entry_row ,if it is 5 and when entry_add_index is randomized and if the value already in test_entries_indices_added for all 5 times then the loop of 5 goes unused .

I have to make sure that , the variable entry_add_index is unique always when sa_entry_row is looped.

if (sa_op_type == ADD) begin
                    sa_entry_row        = $urandom_range(1,5);//Randomizing  The number of times add entries
                    for(int j=0; j<sa_entry_row; j++) begin
                        entry_add_index = $urandom_range(0,($size(test_entries_add)-1));//Randomizing the SA_entry index
                        //this condition will check existing added list in queue and avoid duplication
                        if (!(entry_add_index inside test_entries_indices_added)) begin
                            add_entries_random(test_entries,test_entries_add,entry_add_index);
                            test_entries_indices_added.push_back(entry_add_index);//Queue created to avoid the duplication of the entry
                            added_entry_indices.push_back(entry_add_index); //This is added entries which used as grep in delete entry
                        end
                    end
                end

Thanks

Solution

Solution

dave_59
dave_59
Forum Moderator
5853 posts
May 22, 2018 at 5:49 pm

In reply to syed taahir ahmed:

You still didn't show the declarations of all variables in the code. But I think replacing
entry_add_index = $urandom_range(0,($size(test_entries_add)-1));with

void'(randomize (entry_add_index) with {
    entry_add_index <$size(test_entries_add);
    unique {entry_add_index,test_entries_added};
});
should work.
syed taahir ahmed
syed taahir ahmed
Full Access
68 posts
May 22, 2018 at 6:16 pm

In reply to dave_59:

I'll post the result once trying.

I appreciate your reply Dave, thanks

syed taahir ahmed
syed taahir ahmed
Full Access
68 posts
May 22, 2018 at 9:39 pm

In reply to dave_59:

Quote:
In reply to syed taahir ahmed:

You still didn't show the declarations of all variables in the code. But I think replacing
entry_add_index = $urandom_range(0,($size(test_entries_add)-1));with

void'(randomize (entry_add_index) with {
    entry_add_index <$size(test_entries_add);
    unique {entry_add_index,test_entries_added};
});
should work.

HI Dave ,

One doubt i have with the implementation, since there is condition the number of entry_add_index to be added will be count of $size(test_entries_add).

The query was if the sa_entry_row get a value 5 and we have only 3 entries to be added then the randomization will fail for unique? if i understand correctly.

Thanks

dave_59
dave_59
Forum Moderator
5853 posts
May 23, 2018 at 8:54 am

In reply to syed taahir ahmed:

For the third time, I'll ask for the declarations of the variables involved. How does one determine how many remaining entries are left?

syed taahir ahmed
syed taahir ahmed
Full Access
68 posts
May 24, 2018 at 7:10 am

In reply to dave_59:

Quote:
In reply to syed taahir ahmed:

For the third time, I'll ask for the declarations of the variables involved. How does one determine how many remaining entries are left?

Sorry my bad .. But your solution worked ☺️

Thanks Dave.

© Mentor, a Siemens Business, All rights reserved www.mentor.com

Footer Menu

  • Sitemap
  • Terms & Conditions
  • Verification Horizons Blog
  • LinkedIn Group
SiteLock