Longint

SystemVerilog
,
1

Hi,
When I run the following code I am getting the following result:
y = 4294967295, x = 18446744073709551615
I am not sure how the longint data type works. Can someone please explain?

module t;
int unsigned y;
longint unsigned x;

initial begin
y = 4294967295;
x = 4294967295;
$display(“%0d, %0d”,y,x);
end

endmodule

2

In reply to Naveenkb:

The problem is with your numeric literal. By default, numbers without a size/radix are 32-bit signed decimal integers. Simulators should give you a warning that the literal 4294967295 overflows to -1. Then it gets signed extended to 64-bit value, -1, which becomes a 64-bit unsigned value 18446744073709551615

3

In reply to Naveenkb:

And so to perform the assignment you need to include the size of the literal like so.


y = 32'd4294967295;
x = 64'd4294967295;

By the way, usually the simulator or synthesis compiler will issue a warning in your case.