Logic (FIFOs, etc) in SystemVerilog Interfaces

Hi All,

Is it possible to write logic (FIFOs, etc) inside of SystemVerilog Interfaces?

Could a logic be written inside of modports?

Thank you!

In reply to ldm_as:

Hi All,
Is it possible to write logic (FIFOs, etc) inside of SystemVerilog Interfaces?
Could a logic be written inside of modports?

The items that can be described inside in a SystemVerilog interface or in modports are well defined in 1800’2017. The real question is not what is “possible”, as SystemVerilog can be too flexible, but rather how is it best to use those items.

  • interfaces are best used with UVM and as support logic for verification. Thus, anything related to verification can be inside, including assertions, functions, clocking blocks, assign statements. Those inclusions should not interfere with the functionality of the DUT.
  • modports: Aside from the definition of ins, outs, and inouts you can include setup and hold times. See my reply at
    Do we use modport of an interface when connecting to UVM test? - UVM - Verification Academy

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr


  1. SVA Alternative for Complex Assertions
    https://verificationacademy.com/news/verification-horizons-march-2018-issue
  2. SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  3. SVA in a UVM Class-based Environment
    https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment