Loading a associative array at the same simulation time

SystemVerilog
1

I have a small code as below.I am expecting the size of the associative array to be ‘10’. But it is only ‘1’. Why are the values being overwritten?.
What should be changed to get the size of load_array to be ‘10’.
I’m actually using similar logic in a UVM class method.(write method of analysis port).I’m seeing the same issue there. So, reproduced it in systemverilog for better understanding. Is it because, we are passing all the values at the same simulation time?


program my;

initial begin
for(int i=10;i<20;i++)begin
load_array(i);
end
end
function automatic load_array(int my_int);
bit assoc_arr[int];

assoc_arr[my_int]=1;
$display("size of assoc_array=%0d",assoc_arr.size());
foreach(assoc_arr[i]) $display("assoc_arr[%0d]=%0d",i,assoc_arr[i]);

endfunction
endprogram
2

In reply to kartavya:

========================
Output of the code:

size of assoc_array=1
assoc_arr[10]=1
size of assoc_array=1
assoc_arr[11]=1
size of assoc_array=1
assoc_arr[12]=1
size of assoc_array=1
assoc_arr[13]=1
size of assoc_array=1
assoc_arr[14]=1
size of assoc_array=1
assoc_arr[15]=1
size of assoc_array=1
assoc_arr[16]=1
size of assoc_array=1
assoc_arr[17]=1
size of assoc_array=1
assoc_arr[18]=1
size of assoc_array=1
assoc_arr[19]=1

3

In reply to kartavya:

The variable ‘assoc_arr’ is a local variable to the function ‘load_array’. Its automatic lifetime is only during the call to the function.