Linking output signals of a module after it was formed by EDA netlist writer

Good day, everyone! i had a module, which used interfaces, so in my testbench it was connected like this:
some_module DUT(.reset(reset), .clk(clk), .some_interface(some_interface)).
After EDA netlist writer formed .svo file, interface was replaced with individual signals, using slashes in front of the signals:
some_module(input clk, input reset, input /some_interface.a, /some_interface.b)
i thought, that slashes were just parts of signal names, so i tried to connect that module using those signals:
some_module DUT(.reset(reset), .clk(clk), ./some_interface.a(some_interface.a), ./some_interface.b(some_interface.b))
but compiler said, there should not be a slash there. Does anybody how should i connect DUT and TB then?