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SystemVerilog
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Library dependency

SystemVerilog 4901
srikanthvvs1
srikanthvvs1
Full Access
7 posts
November 26, 2020 at 6:31 am

I'm working on a UVM environment and facing a issue related to compilation (vlogan) to different libraries. It's a bigger environment, here i managed to explain same issue with a short example.

file1: tb1.sv (will set a string in config_db)

module tb1;
  import uvm_pkg::*;
  string str;
  initial begin
    str = "CONFIG DB CHECKER STRING \n";
    uvm_config_db #(string)::set(null,"*","str",str);
  end
endmodule

file2: tb2.sv (will get the string from config db)

[code]module tb2;
  import uvm_pkg::*;
  class test extends uvm_test;
    `uvm_component_utils(test)
    string g_str;
    function new(string name = "", uvm_component parent);
        super.new(name,parent);
        assert(uvm_config_db #(string)::get(this,"","str",g_str))   $display("String retrived from DB %s",g_str);
        else $display("-Error- : Cannot get string\n");
    endfunction
endclass
 
initial begin
  run_test("test");
  end
endmodule[/code][code][code][code][code][code][verilog][/verilog][/code][/code][/code][/code][/code]

when i try to compile above two files in single library its working fine. (below is the command)
vcs -sverilog +incdir+${home}/uvm/src/ $home/uvm/src/uvm_pkg.sv tb1.sv tb2.sv
followed by ./simv

But the issue is when i try to compile those two files into two different libraries (below three commands).

vlogan -sverilog +incdir+${home}/uvm/src/ $home/uvm/src/uvm_pkg.sv tb1.sv -work TB1_WORK
vlogan -sverilog +incdir+${home}/uvm/src/ $home/uvm/src/uvm_pkg.sv tb2.sv -work TB2_WORK

vcs tb2

and when i run "simv" executable the get from config_db fails in tb2.sv below error.

"tb2.sv", 9: tb2.\test::new .unnamed$$_0: started at 0s failed at 0s
Offending 'uvm_config_db#(string)::get(this, "\000", "str", this.g_str)'
-Error- : Cannot get string

I kinda feel like the uvm_pkg is different for two libraries and hence the config_db database is also different.

Can you please let me know a way to use a common package across different libraries.

Replies

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cgales
cgales
Forum Moderator
1556 posts
November 26, 2020 at 8:21 am

In reply to srikanthvvs1:

This Mentor sponsored forum is not for tool related issues. Please contact your vendor support team for additional assistance.

srikanthvvs1
srikanthvvs1
Full Access
7 posts
November 26, 2020 at 11:03 pm

In reply to cgales:

I believe issue is related to systemverilog libraries and packages usage.
Instead can you please explain how to use a common package across different libraries.

Say i compiled uvm_pkg into UVM_LIB
and i need to use this uvm_pkg in other libraries like TB1_LIB, TB2_LIB etc

file1: Compiled to TB1_LIB

module tb1;
import uvm_pkg::*
//other code
endmodule

file2: Compiled to TB2_LIB

module tb1;
import uvm_pkg::*
//other code
endmodule

compiled uvm_pkg.svh to UVM_LIB

When i elaborate it gives below error.

Error-[CFCIL-NS] Cannot find cell in liblist
Cannot find cell "uvm_pkg" of logical library "TB1_LIB" using the following
liblist.
Liblist: DEFAULT TB1_LIB TB2_LIB UVM_LIB

It works fine
I even tried using configuration file, but still same issue

config my_config;
design TB2_LIB.top;
default liblist UVM_LIB TB1_LIB TB2_LIB;
endconfig

cgales
cgales
Forum Moderator
1556 posts
November 27, 2020 at 3:00 am

In reply to srikanthvvs1:

Specifying the location and use of libraries is tool dependent. You will need to contact your tool vendor for additional assistance.

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