LHS concatenation in systemverilog

SystemVerilog
,
1

In the following code how does the LHS concatenation work?


module maindec(input  logic [5:0] op,
               output logic       memtoreg, memwrite,
               output logic       branch, alusrc,
               output logic       regdst, regwrite,
               output logic       jump,
               output logic [1:0] aluop);

  logic [8:0] controls;

  assign {regwrite, regdst, alusrc,branch, memwrite,memtoreg, jump, aluop} = controls;
2

In reply to VIKRANT97:

The opposite direction as if the concat was on the RHS.