Leading clock mismatch in Assertions

[pvr4210]

Hi,
i’m trying to analyze the error, can you pl help me.

property phase_90;
time t1;
(@(posedge clk)('1,t1 = $realtime) |-> @(posedge clk_90)(`PHASE_90 == $realtime -t1));

Error: Leading clock mismatch
Leading clock (2) of the consequent of ‘|->’ operator does not agree with
last clock from the antecedant (1).
Clock (1): posedge clk
Clock (2): posedge clk_90

Thanks,
Venkat

[RahulPatel]

In reply to pvr4210:
Hi
Code looks fine. I simulated the code and it’s working fine for me.

        property phase_90;
                realtime t1;
                (@(posedge clk)('1,t1 = $realtime) |-> @(posedge clk_90)(`PHASE_90 == $realtime -t1));
        endproperty : phase_90
        assert property (phase_90);
  

[kitanisi]

In reply to pvr4210:

In IEEE1800-2005, “@(posedge clk1) … |-> @(posedge clk2) …” is illegal
whereas it is legal in IEEE1800-2009.

Please some compile option to enable IEEE1800-2009 syntax to a simulator.
As to switch to enable 1800-2009 syntax, please ask simulator vendor.

[pvr4210]

In reply to Rahul Patel:

Hi Rahul,

can You pl provide the compilation command which was you used.

Thanks in Advance,
Venkat

[ben2]

In reply to pvr4210:

• compilation command gets into the issue of TOOLS, and we do NOT adress tools in this forum.
• We only address language usage, issues, designs and methodologies.

On your design issue, since the tool does not support the |-> with multiclocking and you are not concerned with both clocks occurring in the same phase, just use the |=>:

property phase_90;
     realtime t1;
     (@(posedge clk)('1,t1 = $realtime) |=> @(posedge clk_90)(`PHASE_90 == $realtime -t1));
endproperty : phase_90
assert property (phase_90); 

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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[pvr4210]

In reply to ben@SystemVerilog.us:

Thanks Ben