A layered testbench architecture for FIFO

SystemVerilog
,
1

Hi, I am looking for assistance on the randomization of the input variables of FIFO.

2

In reply to abhishekk_07:
Lots of options, but one approach is to

  1. Define a transaction class that defines the variables that need to be randomized, along with their constraints.
  2. In the driver class, you randomize the instance of that transaction class and based on the randomized transaction (e,g, push, pop, idle) to call the needed task.
    For example:

package fifo_pkg;
  timeunit 1ns; timeprecision 100ps;
  `define TOP fifo_tb
  typedef enum {PUSH, POP, PUSH_POP, IDLE, RESET} fifo_scen_e;
.../////////////////////////////////////////////////////////////
class Fifo_xactn extends ....;
  rand fifo_scen_e kind;
  rand word_t  data;	// data to push
  rand bit [7:0] idle_cycles;
  rand bit [7:0] reset_cycles;
  time xactn_time;
    
  constraint cst_data {
      data  < 1024;
  }
 constraint cst_idle {
   idle_cycles inside {[1:3]}; 
  }  
 constraint cst_reset {
   reset_cycles inside {[1:10]}; 
  }  

  constraint cst_xact_kind {
    kind dist {
      PUSH := 400,
      POP := 300,
      PUSH_POP :=200,
      IDLE := 30, 
      RESET := 10
    };
  } // cst_xact_kind
...///////////////////////////////////////////////
//////////////////////////////////////////////////
task Fifo_cmd_xactor();
    Fifo_xactn  fifo_xactn_0;  // transaction to get 
    randomize(fifo_xactn_0); 
    case (fifo_xactn_0.kind)
        PUSH :
        begin
          this.push_task(fifo_xactn_0.data);
        end
        POP  :
        begin
         this.pop_task(); 
        end
        PUSH_POP :
        begin
         this.push_pop_task(fifo_xactn_0.data);
        end
        IDLE :
        begin
          this.idle_task(fifo_xactn_0.idle_cycles);
        end
        RESET :
          this.reset_task(fifo_xactn_0.reset_cycles); 
      endcase
.../////////////////////////
/////////////////////////////
 task Fifo_cmd_xactor::push_task (word_t data);
    f_if.driver_cb.data_in <= data;
    f_if.driver_cb.push <= 1'b1;
    f_if.driver_cb.pop  <= 1'b0;
    @ ( f_if.driver_cb);
    f_if.driver_cb.push <= 1'b0;
  endtask : push_task 

  task Fifo_cmd_xactor::pop_task;
    f_if.driver_cb.pop  <= 1'b1;
    f_if.driver_cb.push <= 1'b0;        
    @ ( f_if.driver_cb);
    f_if.driver_cb.pop  <= 1'b0;
  endtask : pop_task

  task Fifo_cmd_xactor::push_pop_task (word_t data);
    f_if.driver_cb.data_in <= data;
    f_if.driver_cb.push <= 1'b1;
    f_if.driver_cb.pop  <= 1'b1;
    @ ( f_if.driver_cb);
    f_if.driver_cb.push <= 1'b0;
    f_if.driver_cb.pop  <= 1'b0;       
  endtask : push_pop_task 
.../////////////////////////

There are of course variations to this.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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