Is it a valid thing to drive the modport signal(which is declared as input)?

SystemVerilog
1

Hi Team,
Is it a valid thing to drive the modport signal(which is declared as input)?.
The snippet is as follows.

interface intf();
logic [7:0]addr;
logic [7:0]data;
logic [7:0]r;
modport dut(input addr,data,output r);
modport tb(output addr, data);
endinterface

module top();
intf intf1();
virtual intf vintf=intf1;//virtual interface.
initial begin
vintf.dut.addr=8’d8;
/vintf.dut.addr=8’d8;
#10
vintf.dut.addr=8’d10;/
end
endmodule

One simulator is complaining the compile time error since the signal is declared as i/p in modport.
Other simulator(From different vendor) is not complaining any error !!(passed).

Please let us know if there are any comments on this issue.

Thanks,
Bhaskar

2

No. It is illegal to drive a signal declared as modport input. Referring to IEEE 1800-2012, modports are explicitly used to provide direction of signals with respect to any module/component. Modports restrict access of any signal for a particular block.

To restrict interface access within a module, there are modport lists with directions declared within the interface. The keyword modport indicates that the directions are declared as if inside the module.

3

In reply to Bhaskar chary:

BTW, you should not be putting dut in your hierarchical reference.A modport is not a scope. It is an access list. You should be using it in your virtual interface variable declaration and when you make the initial assignment from the interface instance name.

 virtual intf.dut vintf=intf1.dut;//virtual interface.

The virtual interface variable declaration states what access is needed, and the instance name with the modport states what access is being given.

Also, the LRM is not very clear how ‘port direction’ should be applied to a virtual interface reference since it is not part of a module port. So implementations vary in interpretation.

4

In reply to dave_59:

Hi Sharvil/Dave,

It’s clear now.Thanks for the explanation.

Thanks,
Bhaskar