This is valid from a SystemVerilog syntax point of view, but I'm not sure this will give you the behavior you are looking for. I'm sure you mean more than just having the ahb_if have an output bit reset feed an input bit reset on the pp_intf.
A port passed by reference works just like a task argument passed by reference. The interface instance will indirectly reference the variable it is connected to. So AHB0.reset and ppi0.reset refer to the same variable; reset1. In other words, reset1, AHB0.reset, and ppi0.reset are considered one shared variable. The same assignment rules for variables apply to this shared variable. You are allowed a single continuous assignment to a variable that acts like a driver, or you can have multiple procedural assignments. When you have multiple procedural assignments, there are no drivers, it is simply last write wins.