Is it possible to pulldown a tri1 signal

Hi,

I am trying to create a pulldown on a tri1 signal.
As the default strength of tri1 is pull and is pulled high, is it possible to pull it down or should I assign a strong signal to it.

Thanks in Advance

In reply to resnathomas:
What you are asking for does not make sense in Verilog. If a net is simultaneously pulled up and down, it resolves to PullX. The purpose of a “pull” on a signal is when no other drivers are driving, it has a known state. What are you trying to achieve?

In reply to dave_59:

Hi Dave,

In my testbench I have declared ‘dp’ port(in usb protocol) as tri1 net. But I want to pull down the port to simulate a usb BC SDP. If I use a pulldown, there will be a contention which will lead to x. So can I use a strong signal to assign to it?

Thanks in Advance!

In reply to resnathomas:

Verilog will allow you to assign a strong0 to a tri1 signal. I don’t know USB well enough to know if this works for you. Note that you cannot model the current sensing ports of USB in Verilog - that is for analog simulation.

In reply to dave_59:

Okay. I shall try this.
Thanks !