Is it possible to create an array from packed structs of different types but of the same size?

Hi,

I wonder if it’s possible to create an array of packed structs of the same size, but different type. I have such structs (more than 20, almost all of them have a different type):



typedef struct packed {
bit [39:32] address;
bit [31:24] x_data;
bit [23:4]  y_data;
bit [3:0]   z_data;
} struct_xyz_t;


typedef struct packed {
bit [39:32] address;
bit [31:8]  a_data;
bit         b_data;
bit [6:0]   c_data;
} struct_abc_t;

struct_xyz_t struct_xyz;
struct_abc_t struct_abc;


Each struct is packed and is 40 bit long.

I’d like to go through all the structs in a loop and do some operation with all of them, and for that, I tried to create an array like this:


logic [39:0] ArrayForStructs[] = '{struct_xyz, struct_abc};

which throws a compilation error saying that the variable type doesn’t match the context type:

error: the type of the variable ‘struct_xyz’ doesn’t match the context type.
xyz.sv:414: : variable type=11netstruct_t
xyz.sv:414: : context type=logic unsigned[39:0]

Is this concept basically possible? Do you maybe have some suggestion how to do that properly?

Many thanks in advance.

Kristof

In reply to KristofK:

This code is legal. Your code worked for me on four different simulators on EDAplayground.com

You might try using an array concatenation {} instead of an assignment pattern '{}.

In reply to dave_59:

Hi Dave,

many thanks for your reply.
Did you try with Icarus? I got this result after changing '{} to {} on EDA playground:

[2021-09-29 10:22:17 EDT] iverilog ‘-Wall’ ‘-g2012’ design.sv testbench.sv && unbuffer vvp a.out
design.sv:21: internal error: I don’t know how to elaborate(ivl_type_t) this expression: {struct_xyz, struct_abc}
design.sv:21: assert: elaborate.cc:2313: failed assertion !is_constant_
Aborted (core dumped)
Exit code expected: 0, received: 1
Done

Compile options are -Wall and -g2012 for Icarus 0.10.

In reply to KristofK:

No. SystemVerilog support in Icarus is limited.