Issue during randomization for dynamic array elements' value

SystemVerilog
1

I am facing an issue in getting correct value of elements of dynamic array

Below is my code :

typedef enum bit [3:0] {
                         YUV,......RAW8,...} data_type_en;


rand data_type_en data_type_1 [];
rand int raw_data_size ;


constraint data_type_1_cn
{
  data_type_1.size == 10
  foreach(data_type_1[i])
  {
    data_type_1[i] == RAW8;
  }
}

constraint raw_data_size_cn
{
   raw_data_size == calc_size();  //Calling function
}

constraint sib_order_cn
{
    solve  data_type_1  before  raw_data_size;
}


function int unsigned calc_size()
 //I added followoing display here to find data_type_1.size
 // which is correctly displayed as 10
 $display("data_type_1.size = %0d", data_type_1.size);

 foreach(data_type_1[i])
 begin
     //I added display to find data_type for each i
    // The value it showed is 0th value i.e. YUV; 
    //while I have assigned RAW8 in constraint

end

endfunction : calc_size

In post randomize method, I get the correct element value for data_type_1 as RAW8. So does this mean that as soon as data_type_1.size is set, the constraint for solve before gets applied and so raw_data_size constraint is applied; though the elements of the array are not assigned the constrained value?
Here the raw_data_size depends on the element value of dynamic array

Thanks