Interview_Question_Regarding_Assertion

The question is :

Whenever signal A goes high, from the next cycle signal B should repeat n no. of times, where n is equal to the value of bit[3:0]C when signal A is asserted.

My solution :


property p;
int local;
@(posedge clk)
($rose(a),local=c)|=> b[*local];
endproperty

Is this the right approach?
If no, then what it is?
If yes, is there any alternative?

In reply to Shubhabrata:
https://verificationacademy.com/forums/systemverilog/sva-repetition-using-variable#reply-99767