Interleaving elements

SystemVerilog
, ,
1

I have a queue with some elements representing number of times a particular input is to be generated. So let’s say we have following queue elements:

my_q = {100,50,50,0};

Now, this queue represents the following:

Input at position-0 should come 2 times
Input at position-1 should come 1 times
Input at position-2 should come 1 times
Input at position-3 should come 0 times

So, the input order should be:

0 (Input-0) – 1 (Input-1) – 0 (Input-0) – 2 (Input-2)

So, I made the following code which works on taking the HCF of number and storing them in a queue:

    initial begin
        int rate[$], mod_rate[$], final_port_seq[$];
        int hcf;
        int num_slot;
        rate = {100,50,50,0}; 
        hcf = find_hcf(rate); // Finds HCF from elements of rate
        foreach(rate[i]) begin
          num_slot += rate[i]/hcf;   // Total number of slots
          mod_rate[i] = rate[i]/hcf; // Get number of occurrences of particular element
        end
    $display("HCF = %0d Number of slots = %0d",hcf, num_slot);    

    // Need to change the following logic:
    for (int i =0; i< num_slot;) begin
      foreach (mod_rate[j]) begin
        if (mod_rate[j] != 0 ) begin // This keeps the sequence 0-1-2-0
          mod_rate[j]--;
          final_port_seq[i] = j;
          i++;
        end
      end
    end

    $display("Final sequence : ");
    foreach (final_port_seq[i]) begin
      $write(" %0d", final_port_seq[i]);
    end
      end
    end // initial
    
      function int find_hcf(int q[$]);
        int min[$];
        int max[$];
        int q_refined[$];
        int flag;
        q_refined = q.find(item) with (item !=0); // 0 is port OFF
        min = q_refined.min();
        max = q_refined.max();
        $display("min = %0d max = %0d",min[0],max[0]);
        for(int i =min[0];i>0;i--) begin
          flag = 0;
          foreach(q[j]) begin
            if(q[j]%i == 0) flag++;
          end
          if(flag == q.size()) begin find_hcf = i; break; end
        end
      endfunction

The code works fine as far as slotting is concerned and I got the following output:

    output:
    min = 50 max = 100
    HCF = 50 Number of slots = 4
    Final sequence : 
     0 1 2 0

But I want to interleave the queue elements and get the output as follows:

    Final sequence : 
     0 1 0 2

Can anyone tell me what kind of logic I need to implement to have interleaved queue elements? The input rate elements can be any other sequence also.

2

In reply to rahulcodesinverilog:

You have not explained your algorithm very well. Are you using the words slot, input, position interchangeably? How does 100,50, 50, 0 turn into 2,1,1,0. I see there is a relationship, but you never defined it. What defines the output you are expecting.

3

In reply to rahulcodesinverilog:

Is your final sequence fixed to “0 1 0 2”. If yes, on what basis are you fixing it?
If my_q = {200,50,100,150}; i.e, when mod_rate[i] will be {4, 1, 2, 3}, what will be your expectation on output? It makes more sense not to have fixed order and let the order be random given the number of times for each port (Unless the specification fixes it for some reason). Specify more inputs, and the expected outputs for each input to get needed help.

And, what is the reason for choosing HCF way to decide the weights? Is it not the same 100:50:50:0 in that order (for 0, 1, 2, 3 ports)? i.e., 2:1:1:0. If that is the case, code can be simplified instead of using HCF calculation.

4

In reply to S.P.Rajkumar.V:

There are four inputs to DUT.

The queue contains input rates/frequencies of input. So, in a bunch of 4 slots (4 clock cycles), if my_q is {100,50,50,0}, then the input-0 should come twice as much as input-1 and input-3. And input-4 should not come. Also, the input-0 should be interleaved between the other two inputs.

Here I am taking HCF of inputs to determine how many slots must be occupied for a particular input and then arranging them in a round-robin fashion. But I want them to be arranged in an interleaved fashion.

Let me know if it clears the doubt or not.

5

In reply to rahulcodesinverilog:

Is it that the input-0 always to be interleaved irrespective of the input rates? Or, would you like to interleave the port that has the highest rate?
Specify few scenarios of i/p rates and corresponding o/p expected sequences as requested in the previous post.