could you please provide the clarifications whether interfaces are synthesizable in system verilog. and if always and initial blocks can exist in interface, why we need module as everything can be written in interface.
In reply to srbeeram:
Assuming we are talking about not virtual interfaces. Yes interfaces are synthesizable and you can use alwasy/ff/comb and initial begin syntax along with continuous assignments as well. Tasks and functions can be declared.
The main different between modules and interfaces is:
an interface can be inst into a module (as ports) a module cannot be inst into an interface:
For instance…
“Instantiation of module ‘p’ is illegal.
Interface “myif” has a module instantiation which is not allowed.”
A module doesn’t know the concept of modports for instance. There are many advantages (reusability and encapsulation) of using interfaces but limitations as well even if they are considered “like a module” they cannot fully used like a module.
Regards
In reply to Rsignori92:
Hi Rsignori92 thanks for clarifications. why we need module as we can have only interfaces.
In reply to srbeeram:
We cannot have only interfaces, even if they can encapsulate whatever a module will encapsulate. During SYNTH you still need a module as a wrapper to run SYNTH efficiently.
On top of that while running SYNTH since interfaces are used on the PORT declaration, since they are as per definition a simple collection of wire, always/ff/comb blocks used internally are not captured by the SYNTH tool resulting into an empty module (with ports)
interface uuiif (
input logic clk,
input logic reset,
input logic d,
output logic q
);
always_ff @(posedge clk or posedge reset) begin
if(reset) q <= '0;
else q <= d;
end
endinterface
module p(uuiif iif);
endmodule
Using Mentor Precision you will get:
module p ( \rtlc_iif.clk , \rtlc_iif.reset , \rtlc_iif.d , \rtlc_iif.q ) ;
input \rtlc_iif.clk ;
input \rtlc_iif.reset ;
input \rtlc_iif.d ;
output \rtlc_iif.q ;
endmodule
This instead would work but TOOLS could complain (for instance I found Mentor interprets async reset as CLK stating that there is a multi-clocked block).
// Code your design here
interface uuiif (
input logic clk,
input logic reset,
input logic d,
output logic q
);
task ff;
if(reset) q <= '0;
else q <= d;
endtask
endinterface
module p(uuiif iif);
always_ff @(posedge iif.clk) begin
iif.ff;
end
endmodule
Hope this clarifies. Regards
In reply to srbeeram:
Another way to think of this is that design units (modules, interfaces and packages) are just ways of creating containers of behaviors. As long as the behaviors are synthesizable, it should not matter how these behaviors get connected together.
However, SystemVerilog has rules about how you compose/elaborate a design. There has to be at least one top-level module, and that module creates dependancies on other design units by instantiating other modules and interfaces, connecting interface ports, and importing packages. Those dependancies create recursive dependancies and that determines what is needed to elaborate the full design for simulation or synthesis.
The original intent of an interface was simply a defined set of port connections that would be connected through module ports. But over time, more module like-features got added in making the distinction less obvious.
Good article on the topic
https://www.researchgate.net/publication/221187603_SystemVerilog_Interface_Based_Design