Interface Port connection through a generate or array instance

SystemVerilog
, ,
1

Hello,

I am trying to access an interface which is bind of a module but that module instantiated through generate block. I am getting following error:

Illegal interface port connection through a generate or array instance (tb.u_wrapper1.u_wrapper2.ret.u_inside_generate.sample_if)

Here is reduced code to reproduce the issue:

interface sample_interface(
  in1, op1
);
  input  [3:0] in1;
  input [31:0] op1;
endinterface : sample_interface

module checker_m(
  sample_interface actual_if
);
endmodule : checker_m

module inside_generate();
endmodule : inside_generate

module wrapper2();

  parameter GEN_PARAM = 2;

  generate
    if(GEN_PARAM == 2) begin : ret
      inside_generate u_inside_generate();
    end
  endgenerate

endmodule : wrapper2

module wrapper1();
  parameter GEN_PARAM = 2;
  wrapper2 #(.GEN_PARAM(GEN_PARAM)) u_wrapper2();
endmodule : wrapper1

module tb();
  
  bind inside_generate sample_interface sample_if(.*);

  bind inside_generate sample_interface check_if();

    bind wrapper1 checker_m u_checker (
      /// How can I access sample_if, which is bound to inside_generate module and 
      ///            that module gets instantiated through generate block
      .actual_if (u_wrapper2.ret.u_inside_generate.sample_if)
    );

  wrapper1 u_wrapper1();
endmodule : tb