Interface connections

SystemVerilog
,
1

Hi,

I want to connect a dut to interface as below,


interface my_if;
endinterface : my_if

module my_dut(my_if in_if[0:3]);
endmodule : my_dut

module top();
  my_if if_1[0:3]();
  my_if if_2[0:3]();

  my_dut dut (.in_if ({if_1[0], if_2[1:3]}));

endmodule : top

I need to connect 0th port of interface if_1 to 0th port of in_if of dut and remaining respected ports of in_if should be connected with respected if_2 ports.

I am getting ‘Illegally connected interface port’. How can fulfill this expectation?

2

Interface cannot be composed like that. You are going to find many limitations with interfaces and will have to stick with simple situations.

Your options are to

  1. break up the interface port array of my_dut into individual ports
  2. create an intermediate module that takes in the two arrays of interfaces and combines them into a single array of interfaces.
  3. use arrays of signals without the array of interfaces. Then you can use assignment patterns to compose your arrays.

Unfortunately, I do not have the time to train you on all these techniques or provide examples. You might consider contacting your vendor for additional help.