Hi,
Is it possible to convert a virtual class to interface class in systemverilog? to implement multiple inheritance
module test();
interface class FSL;
//int a;
endclass
interface class IFC extends FSL;
//int b;
endclass
class a;
endclass
class IFC_TEMP implements IFC;
int a,b;
endclass
initial begin
IFC_TEMP temp;
temp = new();
temp.a = 10;
temp.b = 20;
$display(temp.a);
$display(temp.b);
end
endmodule : test
I want to convert virtual to interface class?
thanks
Sanjaikumar Kannan