the DUT specification is a dual port ram with inputs data_in(64 bits),write_address(12 bits),read_address(12 bits),clock and 2 control signals write and read.The output is data_out(64 bits).
so I did not understand the below interface code we have defined 4 clocking block inside it .2 for write driver and read driver (1 for read driver and write driver) and 2 for write monitor and read monitor(1 for write monitor and 1 for read monitor).
The driver I understand that it is providing input to the dut so all signals except data_out are taken as output because we are driving them as input to dut .But when it comes to the read monitor it shows that it monitors the signal rd_address,read, data_out and similarly for write monitor it monitors wr_address,write,data_in.Monitor will monitor the outputs that we are getting from dut right??.And only output we have is data_out from dut so it should monitor only that signal right.but here it says that it is monitoring the inputs to the dut as well. what is the reason that it is monitoring the input the dut and how it is monitoring also I dont understand.
interface ram_if(input bit clock);
logic [63:0] data_in;
logic [63:0] data_out;
logic [11:0] rd_address;
logic [11:0] wr_address;
logic read;
logic write;
clocking wr_drv_cb@(posedge clock); // write driver
default input #1 output #1;
output wr_address;
output data_in;
output write;
endclocking: wr_drv_cb
clocking rd_drv_cb@(posedge clock); //read driver
default input #1 output #1;
output read;
output rd_address;
endclocking: rd_drv_cb
clocking rd_mon_cb@(posedge clock); //read monitor
default input #1 output #1;
input read;
input rd_address;
input data_out;
endclocking: rd_mon_cb
clocking wr_mon_cb@(posedge clock); // write monitor
default input #1 output #1;
input write;
input wr_address;
input data_in;
endclocking: wr_mon_cb
modport WR_BFM (clocking wr_drv_cb);
modport RD_BFM (clocking rd_drv_cb);
modport WR_MON (clocking wr_mon_cb);
modport RD_MON (clocking rd_mon_cb);
endinterface: ram_if