Hello,
My name is Ketan Dhimmar and currently doing Masters in VLSI and Embedded system design. My project is based on Verification. and for that I am using questa sim 6.6d.
Now,in my project, I want to integrate C model and Verilog using PLI. For understanding, I am taking example of this fibonacci…" C:\questasim_6.6d\examples\verilog\pli\fibonacci". in which i found some problems.
First of all, The verilog program used some data types of system verilog which gives error while doing simulation. I have removed that error by copying whole .v code into .sv file. The problem with ‘C’ file. can you suggest me how can I integrate C model with System Verilog. while adding C file to the project it gives following error.
**** Error: (sccom-95) Your installation directory does not contain the appropriate GNU C++ compiler. Download and install the tarball from the ftp site (gcc-4.2.1-mingw32vc9.zip).**
how I can resolve it? I have already downloaded it but dont know where to paste it.
The best way to get support for any tool issue is to contact your vendor’s support site or field representative. They are the tool experts and will be able to answer any installation or usage issues that you encounter.
To install GCC, you simply unzip the GCC tarball into the main installation directory of Questasim.
Also, the script used to run the example (doit.sh) accounts for the SystemVerilog constructs in the source code by passing the “-sv” argument to the compilation command so you don’t need to rename the .v file.
In reply to cgales:
Hello,
Thank you for your reply. but still I am not clear. I seen doit.sh file and found “-sv” argument. But whenever I compile fibonacci.v file. I got following errors :
**** Error: C:/questasim_6.6d/examples/verilog/pli/fibonacci/fibonacci.v(21): near “[”: syntax error, unexpected ‘[’
** Error: C:/questasim_6.6d/examples/verilog/pli/fibonacci/fibonacci.v(23): near “=”: Syntax error.
** Error: C:/questasim_6.6d/examples/verilog/pli/fibonacci/fibonacci.v(25): near “;”: Syntax error.
** Error: C:/questasim_6.6d/examples/verilog/pli/fibonacci/fibonacci.v(26): near “=”: Syntax error.
** Error: C:/questasim_6.6d/examples/verilog/pli/fibonacci/fibonacci.v(27): near “=”: Syntax error.
** Error: C:/questasim_6.6d/examples/verilog/pli/fibonacci/fibonacci.v(28): near “=”: Syntax error.
** Error: C:/questasim_6.6d/examples/verilog/pli/fibonacci/fibonacci.v(48): near “++”: Operator only allowed in SystemVerilog.
** Error: C:/questasim_6.6d/examples/verilog/pli/fibonacci/fibonacci.v(57): near “++”: Operator only allowed in SystemVerilog.
** Error: C:/questasim_6.6d/examples/verilog/pli/fibonacci/fibonacci.v(70): Undefined variable: results.
** Error: C:/questasim_6.6d/examples/verilog/pli/fibonacci/fibonacci.v(71): near “++”: Operator only allowed in SystemVerilog.
** Error: C:/questasim_6.6d/examples/verilog/pli/fibonacci/fibonacci.v(77): near “++”: Operator only allowed in SystemVerilog.
** Error: C:/questasim_6.6d/examples/verilog/pli/fibonacci/fibonacci.v(78): BEGIN - END required around task/function statements**
what I am doing here is,
creating a new project, adding existing file (only 1 fibonacci.v file) and then compile it…then got above errors. Now if I change whole file .v to .sv there is then no problem with compilation.
Did I do wrong compilation ? or do I have to add more files in a project.? Please Help me.
Thannks & Regards,
Ketan Dhimmar
Questasim will compile a file assuming that the language extension is correct. Since the file is named with a .v extension, pure Verilog is assumed. The ‘-sv’ compilation option will tell the compiler that the file contains SystemVerilog and the extension is ignored.
If you use the Questasim Project Manager, you need to right click on the file and tell Questasim to use SystemVerilog instead of the default language syntax.
However, in this case, renaming the file with a .sv extension is probably a good thing to do, so there is no issue doing what you did.
In reply to cgales:
ok thank you. one more thing, do I need to add ‘C’ file also to an existing project and compile both the files (.sv and .c) simultaneously or something else? when I am compiling both the files simultaneously I got error as I mentioned in my first message about GCC. I still didn’t get this :
To install GCC, you simply unzip the GCC tarball into the main installation directory of Questasim.
here which is main directory of questasim ? can you tell me exact path??
one more thing, after successful compilation of “.sv” file, I am getting following warning :
# ** Warning: (vsim-PLI-3003) C:/questasim_6.6d/examples/verilog/pli/fibonacci/fii.sv(55): [TOFD] - System task or function ‘$fibonacci’ is not defined.
and when I run the program and map signals into the wave window, The output “y_l” is always zero.
why is it so? is it something like I am missing to link SystemC file with “.sv” file??? If it is, then how to link with it.Please help me by giving answer of my both the questions.
You need to read the Questasim documentation. The Questasim user manual provides all the steps required to do what you want to accomplish.
Hi Ketan Dhimmar
Try using http://www.edaplayground.com/ to compile your project!
Hope this works
-BR
Hash
In reply to Hash:
Thank you for reply. I have downloaded modelsim student edition from your site. Now, I am able to compile both the program with no GCC error. but when I simulate it, I am getting following error :
# ** Warning: (vsim-PLI-3003) C:/questasim_6.6d/examples/verilog/pli/fibonacci/fii.sv(55): [TOFD] - System task or function ‘$fibonacci’ is not defined.
How can i resolve this error??