Integrate with PSL and SV

SystemVerilog
,
1

Hello all,
Can i integrate with the SV and PSL.
If yes ,How to integrate with the SV and PSL?
Regards
Rajaraman R

2

In reply to Rajaraman R:

Although PSL was originally developed with language independent support, SystemVerilog assertions (SVA) is what is supported by most tools in that language. You might be able to use PSL with VHDL and bind that in with your SystemVerilog design.

You will need to contact your tool vendor for any mixed language support.