Instance Based coverage

SystemVerilog
,
1

Hi Dave,

I have the following requirement, for which I am not sure how do I implement the coverage.


module my_cov {
   input logic[15:0]   position,
   };

   covergroup cg_en;
      cp_position position {
        bins one_hot[16] = {[0:15]};
      }
   endcovergroup

  initial begin
      cg_en = new();
   end

  always @ (some_cond) begin
     cg_en.sample();
  end

endmodule


Now this module my_oov is bound an RTL module which is instantiated 4 times. 

My requirement is as below:

In Instance # 0 of the coverage module, in my covergroup, I am interested in only values [0:3]. Rest I would like to ignore or not create.
In Instance # 1 of the coverage module, in my covergroup, I am interested in only values [4:7]. Rest I would like to ignore or not create.
In Instance # 2 of the coverage module, in my covergroup, I am not interested in any values. I do not mind to ignore all the values or dont construct the cover group at all.
In Instance # 3 of the coverage module, in my covergroup, I am not interested in any values. I do not mind to ignore all the values or dont construct the cover group at all.

Is there a way to achive/implement such a requirement?

Thanks,
Madhu

2

In reply to mseyunni:

module my_cov #(int B[] = '{0}) (
  input logic[15:0]   position, bit clk
);
 bit some_cond;
   covergroup cg_pos;
      coverpoint position {
        bins one_hot[] = B;
      }
   endgroup
 
  cg_pos cg;
  initial begin
      cg = new();
   end
 
  always @ (clk) begin
     cg.sample();
  end
 
endmodule

module top;

  bit clk;
  logic [15:0] pos;

initial #5 clk=1;


  my_cov #(.B('{0,1,2,3})) U1 (pos,clk);
  my_cov #(.B('{4,5,6,7})) U2 (pos,clk);
  my_cov #() U3 (pos,clk); // coverpoint will be empty
  my_cov #() U4 (pos,clk);

endmodule

B does not have to be a parameter. I can be a variable as long as it gets set before constructing the covergroup.

3

In reply to dave_59:

Thank you so much Dave it works !