Input variable is being taken as 1 bit instead of parametrized width

SystemVerilog
,
1

I am running below code in vcs-
module param #(width=16)(a,b,c);

input bit [width:0] a,b;
output bit [width:0] c;

initial begin
c=a+b;
$display(“a is %h and b is %h and c is %h and time is %t”,a,b,c,$time);
end

endmodule

module adder;

//int a,b,c;
param #(7) p1 (8’ha0,8’h11,c); //line 16
param #(9) p2 (10’h200,10’h14,c); //line 17
endmodule

output of line 16 and 17 is same. output is a is 000 and b is 000 and c is 000 and time is 0.
Why variable a and b’s parametrized widths are not being taken?

2

I believe there is a race condition here.
I tried printing variables after 1ns delay, which yielded me correct expected values.
Even changing $display to $strobe also works.

3

In reply to naveensv:

Thanks naveensv. It is working with delay. But i am not able to understand the reason behind race condition.

4

initial block executes at start of simulation and it does not depends on any sensitivity list.
It is possible when initial block executed, it could have taken “0” as default value for all variables. Here we can say you are facing an issue of “non-determinism” which is simulator specific.

If you give a delay it will work fine, as at this point your variables will be assigned to proper values(what you have provided).

Solution:
If you write same code in a always block(replacing initial block), your code will work.

Kiran

5

In reply to kiru2006:

Thanks kiru2006 for explanation. With always block, code is working.