In reply to laureen.giac:
You were the one that used the term 'register', which is a component that stores state. Maybe you just meant to say 'reg' data type, which is just a 4-state signal.
Also, when you say 'Verilog,' do you mean the predecessor to the SystemVerilog language? Or are you using them as interchangeable terms. There are different answers to your original question depending on which language you meant.