Input port as register in Verilog?

SystemVerilog
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I’m working on a script to generate automatic Verilog designs and testbenches covering reg data types. So Is there a scenario where we can declare an input port in Verilog as register? thanks

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In reply to laureen.giac:

In Verilog, no; in SystemVerilog, yes. But the ‘reg’ data type does not always map to a ‘register’ in terms of hardware. That’s why SystemVerilog renamed the ‘reg’ data type to ‘logic’.

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In reply to dave_59:

In reply to laureen.giac:
But the ‘reg’ data type does not always map to a ‘register’ in terms of hardware…

Thanks Dave, but you could you please explain that phrase a bit more?

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In reply to laureen.giac:

You were the one that used the term ‘register’, which is a component that stores state. Maybe you just meant to say ‘reg’ data type, which is just a 4-state signal.

Also, when you say ‘Verilog,’ do you mean the predecessor to the SystemVerilog language? Or are you using them as interchangeable terms. There are different answers to your original question depending on which language you meant.

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In reply to dave_59:

Hi Dave,

thanks again. I did mean the reg data type in both Verilog and SystemVerilog.

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In reply to laureen.giac:

See Usage of Var | Verification Academy and http://go.mentor.com/wire-vs-reg