Input plusarg to store weighted distribution

SystemVerilog
,
1

Hi all,

I am trying to find an easy way to implement the following:

User will input a plusarg like: +instr=RD-30:WR-50:NOP-10

The sequence has a queue called all_instr. It should parse the plusarg above and populate “all_instr”.

e.g.
typedef struct {
string itype;
int iwt;
} instr;

instr all_instr[$];

function populate_all_instr();

//This function should set all_instr queue’s members by parsing the user input

endfucntion

2

You can pass the plusarg value from the command line and catch that value inside your sequence in a variable, later you can use that variable inside a loop where you generate the transactions.

For example,

      if($value$plusargs("WR=%d",wr)) begin
        `uvm_info (get_type_name(),$sformatf ("wr = %0d", wr), UVM_DEBUG)
      end else begin
        wr = 50;
        `uvm_info (get_type_name(),$sformatf ("wr = %0d", wr), UVM_DEBUG)
      end
        rd = 100 - wr;
        `uvm_info (get_type_name(),$sformatf ("rd = %0d", rd), UVM_DEBUG)
randcase
  wr : begin
      `uvm_do_on_with(wseq, seqr, 
      {
        addr inside {[1:10]};
        data == 100;
      })
  rd : begin
      `uvm_do_on_with(rseq, seqr, 
      {
        addr inside {[1:10]};
      })
endcase
3

I am specifically trying to find how I can store the following in a string-int pair.

+instr=RD-30:WR-50:NOP-10

In reply to megamind:

4

In reply to 1978bubun:

It would be much easier to read this from a file using $fscanf. Doing it from the command line requires a number of steps (untested)

string line;
string pairs[$];
// Read the command line string using $value$plusargs
if ($value$plusargs("instr=%s",line)) begin
   // split the line into instructions
   uvm_split_string(line,":",pairs);
   foreach(pair[ins]) begin
      string i_w[$]
      // split the pair into instruction/weights
      uvm_split_string(pair[ins],"-", i_w);
      if (i_w.size == 2) 
        all_instr.push_back(instr'{itype:i_w[0], iwt:i_w[1].atoi()};
      else 
        // something is wrong
   end
end
5

In reply to 1978bubun:

An excellent paper on similar approach was presented by Jermey at various forms including DVTalk http://verifnews.org/conferences-events/dvtalk/dvtalk-oct6/

You can google that paper or fetch ut from:

https://www.synopsys.com/news/pubs/snug/2014/silicon-valley/MB6_Ridgeway_Pres_User.pdf

BTW - I personally am not a big fan of this technique as it makes your constraint solver and regression beyond SV code into scripts/Makefiles. But you may like it.

Srini