Input to an arrayed out instance

SystemVerilog
,
1

I’m netlisting a certain schematic, with a systemverilog netlister. I have models for every block. By design, there are some cells that are arrayed out. I’m struggling with how to connect these things, arrays would produce a “Assignment pattern - Illegal AP context [SystemVerilog]” error, and nothing else comes to mind. For example:

var real in0, in1, in2, in3;
var real out [3:0];

inverter I0[3:0] ('{in0,in1,in2,in3},out);

Array of in0-in3 will create an error, while “out” like this won’t. I can resort to creating some temporary variables, but that beats the point of netlisting everything.

Thanks,
Jovan

2

In reply to jovanmit:

Arrays of instances were never extended to be used with anything other than integral bit vectors, so you are at the mercy of what your tools have implemented.

You might try:

typedef real real4_t [3:0];

inverter I0[3:0] (real4_t'{in0,in1,in2,in3},out);