Inout port in interface

SystemVerilog
1

What is the best way to implement a inout port in interface.
While using inside interface, let inout logic [15:0] IO;
Its giving error.

2

In reply to Abhisek Sarkar:

Please show the complete port declaration and the actual error.

3

In reply to Abhisek Sarkar:

define “wire” instead of “logic” for signals under interface block.

4

In reply to javatea:

With the code shown,
inout logic [15:0] IO; is equivalent to
inout wire logic [15:0] IO;.