In reply to cgales:
Got it, I have made some changes to my sequence item and base sequence as below. Also for the READ where I need directed values from the previous WRITE transaction(for score boarding purpose), I can make changes according your inputs. Your valuable inputs are helping me to move, thank you for that.
Please let me ask further for the WRITE transaction randomization, where I want to understand more about it to make sure I am not doing anything wrong or want to follow proper guidelines.
THIS IS MY sequence item WITH CONSTRAINTS,
class axi_seq_item_base extends uvm_sequence_item;
rand eAxiKind kind;
rand bit [8:0] id;
rand bit [32:0] addr;
rand bit [255:0] data [];
rand bit [4:0] length;
rand bit [2:0] size;
rand bit [3:0] qos;
rand bit [5:0] user;
rand eAxiBurstKind burst;
rand eAxiRspKind resp;
rand bit wait_for_rsp;
constraint c_data_array {
data.size() == length+1;
}
constraint c_max_length { length < 16; }
constraint c_align { addr % 2**size == 0; }
constraint c_burst { burst inside {axi_type_pkg::FIXED, axi_type_pkg::INCR,axi_type_pkg::WRAP};}
constraint wrap_lenght {if (burst == axi_type_pkg::WRAP) length inside {1,3,7,15};}
constraint c_dj_bytes {if (burst == axi_type_pkg::WRAP) {2**size *(length+1) == 64};}
constraint c_dj_alow {if (burst == axi_type_pkg::WRAP) {addr[4:0] == 0};}
constraint c_dj_user {if (burst == axi_type_pkg::WRAP) {addr[11:6] == user[5:0]};}
//constraint c_dj_bit5 {if (burst == axi_type_pkg::WRAP) {addr[5] == !addr[5]};}THIS IS MY BASE SEQUENCE, HERE I DON'T USE ANY CONSTRAINT,
class axi_base_seq extends uvm_sequence #(axi_seq_item);
string tID;
rand axi_type_pkg::eAxiKind s_kind;
rand bit [8:0] s_id;
rand bit [31:0] s_addr;
rand bit [255:0] s_data[];
rand bit [4:0] s_length;
rand bit [2:0] s_size;
rand bit [3:0] s_qos;
rand bit [5:0] s_user;
rand eAxiBurstKind s_burst;
rand bit s_wait_for_rsp;
task body();
req = axi_seq_item::type_id::create("req");
`uvm_info(tID,$sformatf("sequence RUNNING id=%x addr=0x%0x length=%d", s_id, s_addr, s_length),UVM_DEBUG)
start_item(req);
if (!req.randomize() with
{
addr == s_addr;
length == s_length;
size == s_size;
burst == s_burst;
id == s_id;
kind == s_kind;
addr == s_addr;
wait_for_rsp == s_wait_for_rsp;
foreach(s_data[i]) data[i] == s_data[i];
})
`uvm_error(get_type_name(), "Randomize failed")
finish_item(req);
`uvm_info(tID,$sformatf("sequence COMPLETE id=%x", s_id), UVM_DEBUG)
endtask : body
axi_base_seq axi_wseq;
repeat (10) begin
`uvm_do_on_with(axi_wseq, axi_seqr,
{
s_kind == axi_type_pkg::WRITE;
s_id inside {[axi_seqr.cfg_h.id_lo:axi_seqr.cfg_h.id_hi]};
s_addr inside {['hb0000000:'hbfffffff]};
s_length inside {[0:axi_seqr.cfg_h.max_length]};
s_size inside {[0:axi_seqr.cfg_h.max_size]};
s_burst == axi_type_pkg::INCR;
s_wait_for_rsp == 1;
})
endFor some iteration randomization works and for some iteration randomization fails and produces below error,
axi_base_seq.sv: The randomize method call failed. These constraints contribute to the set of conflicting constraints:
constraint c_align { addr % 2**size == 0; } (axi/axi_seq_item.sv)
addr == s_addr; (./axi/axi_base_seq.sv)
size == s_size; (./axi/axi_base_seq.sv)
These variables contribute to the set of conflicting constraints:
state variables:
s_addr (3033572225) [./axi/axi_base_seq.sv]
s_size (4) [./axi/axi_base_seq.sv]
rand variables:
addr [./axi/axi_seq_item.sv]
size [./axi/axi_seq_item.sv]I thought I was doing it correct , as from the virtual sequence , I gave the ranges to different control fields and then randomized it, shouldn't it work?
Can you please explain me if the constraint need to be updated here or I need to enhance constraint in the axi_base_seq(and if that need to be matching with axi_seq_item constraints) or basically what I need to take care to avoid failing randomization?
Thank you and Best regards.