There is enough documentation/articles on advantages vs disadvantages of Inheritance over Composition in OOP (C++ world). I do not see papers OR articles that clearly demonstrate the advantages/disadvantages of Inheritance over Composition in System Verilog world. There are some books like Chris Spears book on System Verilog touches on it, doesn’t dwell in depth. As test-bench architect using System Verilog, what are the aspects that one needs to consider before choosing Inheritance OR Composition.