Inheritance overridden member - memory allocation issue

SystemVerilog
,
1

Hi,

I want to understand memory allocation while overriding member in concept of inheritance.
My code is -

class a;
  int i = 1;
endclass : a

class b;
  int i = 2;
endclass : b

module top;
  a a1;
  b b1;
  int p1,p2;

  initial begin
    b1 = new;
    a1 = b1;
    p1 = a1.i;
    p2 = b1.i;
  end
  
endmodule

Now I understand here that as there is only one memory created as only one new is called. And b1 is just assigned to a1.
Result - p1 will be 1 and p2 will be 2.

Question - If there was only one memory allocated here, how come i got a1.i as well as b1.i later ?
As per my understanding, If there was only one memory created in this case, ideally either value of i should get overloaded & i should be able to access any one value of i only rather than both.
Please explain me memory allocation while overriding members here…

2

In reply to shahkavish77:
You are correct that only one object gets created, but the type of that object class b, which is extended from class a. When you extend a class type from another class type, that new class type contains everything in both classes. So when you construct an object of a class b type, both int i member variables get allocated. Which i variable you access depends on the class variable used to reference the object.

Please see my SystemVerilog OOP course, especially the second session on inheritance.

3

In reply to dave_59:

Thanks Dave. Got clear idea and superb videos.