Info about .eq() in system verilog

I was writing a testcase in system verilog (UVM) and I came across .eq() method. My gvim editor color coded it to a slight green color suggesting its a system reserved method (or class). I using an exact notation to represent an equalizer where .eq(1) represents equalizer powered on or .eq() represents equalizer powered off.

something like this power_on_modules(.adc(1), .mixer(1), .mux(), .eq() ) // where adc and mixer are powered on and mux and eq are powered off…

I don’t see any problems with this now but I’m curious if this works fine everytime ? and I won’t have any problems in the future when the test environment gets more complicated.

Thanks

It’s not a reserved word or a built-in method of SystemVerilog.

Oh Okay. Then I have no idea why that word is color coded in testcase. Thanks for your help.

  • Sai Pavan Yaraguti