Infinite loop due to signed arithmetic

SystemVerilog
,
1

I have the following piece of code, which is leading to an infinite loop due to comparison issue:


                bit [23:0] offset;
		for(offset='h1000-'h4; offset>='h0000; offset-='h4)
		begin

What can be a suitable alternative?

2

In reply to prashantg:

The code shown is not an infinite loop. Offset will hit 0.

3

In reply to dave_59:

Dave, looks like I made a serious typo. Can you have a look again?

4

In reply to prashantg:

You either declare offset as signed, or use a separate signed loop variable.

for(int loop='h1000-'h4; loopt>='h0000; loop-='h4)
    begin
    offset = loop;