Index resolution in a macro used in a generate block

SystemVerilog
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1

Hi,

I have some issues trying to use a parametrized macro in a generate loop (I guess the issue would be the same in a for loop).
I want to assign some internal signals of my design under test from my TestBench. Those signals are in different instances instantiated from a generate, so I would like to do this in a generate in the TB to avoid having to repeat the code.
In pre-synthesis code, everything work as expected :


`define MY_PATH(IDX)  assign u_dut.gen_my_generate[``IDX``].u_module
generate
    for (genvar i = 0; i < 4; i++) begin : gen_signal_assign
        assign `MY_PATH(i).my_signal = 1'b1;
    end
endgenerate

On the post synthesis netlist, Design Compiler replaced the generates blocks with its own naming convention, the path now looks like this :


u_dut.gen_my_generatex0xxu_module
u_dut.gen_my_generatex1xxu_module
u_dut.gen_my_generatex2xxu_module
u_dut.gen_my_generatex3xxu_module

Modifying my macro to fit this path does not work


`define MY_PATH(IDX)  assign u_dutxgen_my_generatex``IDX``xxu_module
generate
    for (genvar MY_IDX = 0; MY_IDX  < 4; MY_IDX ++) begin : gen_signal_assign
        assign `MY_PATH(MY_IDX).my_signal = 1'b1;
    end
endgenerate

Returns:

Error : could not find u_dut.gen_my_generatexMY_IDX**xxu_module in hierarchy u_dut

The index in the macro is not resolved, and is replaced with the genvar name, as if I called the macro with a string and not with a index representing a value. The index resolution does not seem to happen.

Is it possible to do such construct ?

Best regards,

Nils

2

In reply to nex:

There’s no way within SystemVerilog to iterate over any set of characters embedded in an identifier name. Note that after synthesis flattens and optimizes, it is possible that not all the consecutive names exist. So you are left with doing this manually in a text editor, or some other script to generate the code.

3

In reply to dave_59:

In reply to nex:
There’s no way within SystemVerilog to iterate over any set of characters embedded in an identifier name. Note that after synthesis flattens and optimizes, it is possible that not all the consecutive names exist. So you are left with doing this manually in a text editor, or some other script to generate the code.

Hi Dave, thank you for your answer
I was expecting this kind of limitation but hoped there was a (maybe tricky) way to bypass it.
Good point about the synthesis not preserving the path or instances, this is not the case with my code but it could happen in some case.

Best regards,

Nils

4

In reply to nex:

If all you are trying to do is force certain signals to a constant, you way want to look at your tool’s User Manual for accessing signals by a string name. This requires turning off certain optimizations to keep the signal and its name available in simulation.