`include in a System verilog file

SystemVerilog
,
1

Hi,
In a system verilog file(file1), 1st : I am including a verilog file using include "file2.v" and then, 2nd : I am including another systemverilog file using include “file3.sv”.
Now the file3 is instantiated inside the file1. file3 uses some tasks(eg. “tasklist”) defined in file1, in spite of having these includes, I get an error stating that “Hierarchical name component lookup failed at ‘tasklist’.”

Please help me out!
Thanks in advance!

2

In reply to Saraswati:

You will need to post an example of what you are trying to accomplish. If the files contain different modules or classes, then where the files are included will affect their visibility.

3

Hi Saraswati,

Please make sure that whatever you are using in file3 of file1, it should be defined in file1 before `include “file3.sv”.

Example :

file2.sv :
/////////////////////////START FILE 2////////////////////////////////////////
class child extends base;

function display_child();
$display(“Inside display_child\n”);
endfunction

endclass
/////////////////////////END FILE 2 ///////////////////////////////////////

file1.sv :
/////////////////////////START FILE 1////////////////////////////////////////
class base;
int a;

function display_Base();
$display(“Inside display_Base\n”);
endfunction

endclass

`include “file2.sv” //**file2.sv should be included after file1’s content.If it would have included before class base definition,then it will give error.
**
/////////////////////////END FILE 1///////////////////////////////////////

4

In reply to msshah:

Hi Msshah,
Thank you for the answer, but the issue in my case was something different: I will explain it here so that it is helpful for others:

I had instantiated the module correctly & had also included the files in the correct sequence, BUT, was not using the hierarchy to call the task Correctly.

The correct way to use it is (if module contains tasks):

(inside SV module)
module module_inst;
module_inst.task1();
module_inst.task2();
…

Thanks!