Import package based on define

SystemVerilog
, , ,
1

Hi ,

I want to import or use a specific package based on the macro value of `define

for example if I `define PACKAGE_TO_USE PACKAGE_1

i would like to import only PACKAGE_1

something like (C equivilant)

`ifeq PACKAGE_TO_USE 1
import package_1::*;
`endif
`ifeq PACKAGE_TO_USE 2
import package_2::*;
`endif

Thanks,
Guy

2

In reply to Guy Levenb:

There is no `ifeq in SystemVerilog; the complexity of its datatypes makes it difficult to evaluate in a preprocessor.

Why not use

`define  PACKAGE_TO_USE package_1

import `PACKAGE_TO_USE::*;

Note that most tools allow you to put different versions of the same package into different libraries, and then you can choose which library to use when compile the code that imports it.

3

In reply to dave_59:

Thank you Dave.
That approach solved my issue.
I also tried to use the other approach you suggested, to have different packages with same name,
But I think the way we define +include+ might cause one package to use another package