Implicit port connection

SystemVerilog
,
1

Hi All,

In below example, my intention to control DUT inputs from testbench using interface handle.
Plan is to avoid individual port mapping, and to leverage implicit port connection.

But I see that without “assign reset = intf.reset;” reset port updates are not visible at DUT.

My assumption is implicit port connection establishes below path : dut_intf.reset → reset → DUT.reset.
Please correct me if wrong.

//***************************
interface dut_itf;
 logic clock,reset;
endinterface

//***************************
module DUT(input clock, reset);
 initial  $monitor("Value reset = %0h",reset);
endmodule

//***************************
module testTop;

 logic clock, reset;

 DUT d1(.*);
 dut_itf intf(.*);
 

 //assign reset = intf.reset;

 initial begin // Eventually will be a UVM TB, which uses vif handle of intf to control DUT signals
   intf.reset = 1;
   #100 intf.reset = 0;
 end

endmodule
2

In reply to g8Grundeller:
Please use code tags making your code easier to read. I have added them for you.

Your problem is your interface has no ports to connect. You need to add ports so the connection needs can be make the same as a module-to-module connection.

interface dut_itf(output
 logic clock,reset
                 );
endinterface
3

In reply to dave_59:

Thanks Dave.It worked.

Also will ensure to use code tags in future posts. Thanks for updating the current post.