Implication Constraint Variation

SystemVerilog
,
1

Hi ,

  1. I have following codes ::

class Busop ;
rand bit [1:0] addr ;
rand bit [1:0] io_space_mode ;
constraint c_io { io_space_mode -> ( addr == 3 ) ; }
endclass
Busop b ;
initial begin
b = new() ;
repeat(5)
if ( b.randomize() with { IN-LINE Constraint  } ) // I try combinations of IN-LINE Constraint
begin
$display("Success with %p",b);
end
end

(a) If IN-LINE Constraint is :: io_space_mode == 1 ;
I observe output is always '{addr:3, io_space_mode:1}
(b) If IN-LINE Constraint is :: io_space_mode == 0 ;
I observe that in Output io_space_mode is always 0 but addr can be any value from 0 to 3
2. [II] If I modify Constraint to :: constraint c_io { !io_space_mode → ( addr == 3 ) ; }
(a) If IN-LINE Constraint is :: io_space_mode == 0 ;
I observe output is always '{addr:3, io_space_mode:0}
(b) If IN-LINE Constraint is :: io_space_mode == 1 ;
I observe that in Output io_space_mode is always 1 but addr can be any value from 0 to 3
Confusion / My Question arises when ::
3. [III] I modify Constraint to :: constraint c_io { ! ( io_space_mode → addr == 3 ) ; } // I see discrepancy in Simulator Outputs
// ( Some show a Compilation Issue on above Constraint )

(QA) If IN-LINE Constraint is :: io_space_mode == 0 ;
What should be output ?

(QB) If IN-LINE Constraint is :: io_space_mode == 1 ;
What should be output ?

(QC) Is there any issue with constraint III ?

2

In reply to Have_A_Doubt:

Realize that → is both a boolean operator and a constraint expression.

As an operator,
(i → j) is equivalent to
(!i || j). Plug the values you are getting for QA and QB, and that should answer those questions.

For QC, as long as j is an integral expression in the expression
!(i → j) this should be legal. (equivalent to
(i && !j). However if j is a constraint set, like
!(io_space_mode->{addr <4; addr > 0;}). this is no longer legal syntax.

3

In reply to dave_59:

Since ! ( i → j ) is equivalent to ( i && ! j ) I observe ::

(A) Randomization failure since constraint would return 0 ( 0 && ANYTHING is 0 )

(B) io_space_mode is 1 whereas addr is inside [0:2] ( due to ! ( addr == 3 ) )

I have one last question


 io_space_mode -> ( addr == 3 ) ;  can also be written as 
 if ( io_space_mode == 1 ) { addr == 3 ; }

I always wondered when to use if-else constraint and when to use Implication .
The only point that I had was I can write multiple conditions in if-else constraint ( via
if { … } else if { … } else { … } ) .

Can I conclude that if RHS of implication is a constraint , if-else is the correct way ?


!(io_space_mode->{addr <4; addr > 0;} )  // Error 

if ( io_space_mode == 1 ) 
{ addr < 4 ; addr > 0 ; } // If RHS of Implication is a Constraint , if-else is the Solution