Implementation of wait statement inside a fork join block

SystemVerilog
1

what modification is needed to display i value =5,2,7? I am not getting output. Any suggestion will be helpful.

2

In reply to Soumyajit Ghosh:

See https://verificationacademy.com/forums/systemverilog/fork-joinnone-inside-loop

3

In reply to dave_59:
Hi Dave,
I have gone through your link but still my problem is not resolved. I am getting output only for i =0. for i =5,2,7 pointer is stuck at wait statement and I am not getting any output.

4

In reply to Soumyajit Ghosh:

You need to be using a join_none instead of join. Otherwise it gets stuck waiting for a bit to change that never does.

module tb#(int T=8);
  bit [8:0] abc;
  initial
      for(int i=0; i<T; i++)
        fork
          automatic int k = i;
          begin  
            wait(abc[k] == 1'b1);
            $display(i,,k,,,$time);
         end
        join_none
  
  initial
    begin
      
      abc[5] = 1'b1;
      
    #10  abc[2] = 1'b1;
      
      abc[7] = 1'b1;
      end
endmodule
5

In reply to dave_59:

Thanks Dave It worked. I got your point also. Thank you very much for the explanation.