have to implement randomize() function in systemVerilog because the tool I use (model sim) doesn't support this function.
I implemented a basic function in a class with the following member:
bit [15:0] data_xi;
bit [15:0] data_xq;
the basic random function:
function int my_randomize(int seed);
int temp1, temp2;
// temp = $urandom_range(1,11);
temp1 = (($urandom(seed)) + 1);
data_xi = temp1 - 1;
temp2 = (($urandom(seed)) + 1);
data_xq = temp2 - 1;
if(temp1 != 0 || temp2 != 0 )
Now I have to change it to static function which suppose to behave like randomize() with constraints.
I want that the user could write class_name.randomize(), and the function will random all the relevant params.
How can I implement this?