Implementation of randomize()

SystemVerilog
,
1

have to implement randomize() function in systemVerilog because the tool I use (model sim) doesn’t support this function.

I implemented a basic function in a class with the following member:

   bit [15:0]  data_xi;
   bit [15:0]  data_xq;

the basic random function:

 //function my_randomize
    function int my_randomize(int seed);
       int temp1, temp2;
      // temp = $urandom_range(1,11);
       temp1 = (($urandom(seed)) + 1);
       data_xi = temp1 - 1;
       temp2 = (($urandom(seed)) + 1);
       data_xq = temp2 - 1;
       if(temp1 != 0 || temp2 != 0 )
     return 1;
       else
     return 0;
    endfunction: my_randomize

Now I have to change it to static function which suppose to behave like randomize() with constraints.

I want that the user could write class_name.randomize(), and the function will random all the relevant params.
How can I implement this?

2

*In reply to saritr:*I assume you mean a global function not specific to any class.

SystemVerilog does not give you the features necessary to implement randomize() yourself. There is no way to pass constraints as an argument to a function, nor is there a way to interrogate the constraints associated with a class. Function cannot have variable numbers of arguments.

3

In reply to dave_59:

I can pass them as regular inputs (min and max val).

4

In reply to saritr:
I would say that is passing values to a hard coded constraint, not passing the constraint itself.

As I said earlier, there is no way to have a user defined function called for all random variables in a class. So what is the benefit of having this function, versus having users call $urandom_range directly?