Implementation question on below specification, Planned to add assertion for this specification

SystemVerilog
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1

Check Condition:

As per specification between sig1 and sig2,

I am expecting clk1- min-10,max-15;+ clk2-min-5 and max-6;

sig1 will get asserted at clk1 and sig2 also gets asserted on clk1.

Now the expectation is specific number of clock’s between clk1 and clk2.

Can someone help me with the property for this condition?

2

In reply to Verif_Learner_SG:
You can use a variation of property p_2busy shown in my reply at
https://verificationacademy.com/forums/systemverilog/local-variable-sva