Immediate assertions

SystemVerilog
,
1

We were expecting assertion to pass at #5 time units can anyone explain why assertion is failing.

module asertion_ex;
  bit clk,a,b;
   
  //clock generation
  always #5 clk = ~clk;
   
  //generating 'a'
  initial begin
    a=0;
    b=1;
    #5 a =1;
    #15 b=0;
    #10 b=1;
        a=0;
    #20 a=1;
    #10;
    $finish;
  end
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, asertion_ex);
  end
   
  //Immediate assertion
  always @(posedge clk) assert ($rose(a));
 
endmodule

EDA link:

please explain difference between immediate and concurrent assertions, as we can see from above example immediate assertion can also be run over a period of time, confused please explain.

2

In reply to Chandra Shekar N:

Please use code tags making your code easier to read. I have added them for you.

You have a race condition at time 5 because you assign both a and clk to 1 at time 5. But $rose(a) uses the sampled value of a at the beginning of thr time step, so it is still 0.

There is a small overlap in functionality between immediate and concurrent assertions. Realize that an immediate assertion can only evaluate one expression at a single point in time. Concurrent associations are much more powerful with complex temporal expressions.