I'm looking for some ways that can verify the round-robin arbiter without using assertions....maybe use task or function to calculate the expected grant

SystemVerilog
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1

for example ，3 channel namely: A,B and C with reqA, reqB and reqC being the requests
and gntA, gntB and gntC being the grants.

2

In reply to star123:

In term of how to use tasks to emulate SVA, take a look at my paper

Understanding the SVA Engine,
https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2

The task keeps track of the history of the grants and addresses which grant to give.
This is then compared with an immediate assertion.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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